Investigation of gate leakage current in TFET: A semi-numerical approach
dc.Affiliation | October university for modern sciences and Arts MSA | |
dc.contributor.author | Tawfik, N.M.S | |
dc.contributor.author | Shaker, A | |
dc.contributor.author | Sayed, I | |
dc.contributor.author | Kamel, H | |
dc.contributor.author | Salem, M.S | |
dc.contributor.author | Dessouky, M | |
dc.contributor.author | Fedawy, M | |
dc.date.accessioned | 2023-04-24T12:57:28Z | |
dc.date.available | 2023-04-24T12:57:28Z | |
dc.date.issued | 2023-04 | |
dc.description.abstract | Tunneling FET (TFET) has been demonstrated as a favorable candidate to replace con- ventional MOSFETs in low-power applications. However, there are many challenges that should be overcome to efficiently operate the TFET. One of the most limiting factors that can restrict the TFET performance is the gate leakage current. In this paper, the tunneling leakage current through the gate oxide of double gate TFET has been analyzed. The conduction band energy level for gate- oxide-silicon was employed to calculate the tunneling transmission coefficient by utilizing a numer- ical method. To obtain the potential barrier between the gate and the channel surface, a modified analytical pseudo-2D method has been applied to deduce the corresponding surface potential taking into account a precise calculation of depletion regions. Furthermore, the inclusion of the image charge barrier lowering effect is incorporated in calculating the transmission probability through the oxide. Including such an effect shows a significant influence on determining the gate tunneling current. The gate leakage current has been calculated for various bias voltages and equivalent oxide thicknesses. The presented semi-numerical technique shows good agreement within a suitable CPU time when validated and compared against full numerical TCAD simulation. 2023 The Authors. Published by Elsevier B.V. on behalf of Faculty of Engineering, Alexandria University | en_US |
dc.description.uri | https://www.scimagojr.com/journalsearch.php?q=13907&tip=sid&clean=0 | |
dc.identifier.doi | https://doi.org/10.1016/j.aej.2023.03.092 | |
dc.identifier.other | https://doi.org/10.1016/j.aej.2023.03.092 | |
dc.identifier.uri | http://repository.msa.edu.eg/xmlui/handle/123456789/5561 | |
dc.language.iso | en_US | en_US |
dc.publisher | Alexandria University | en_US |
dc.relation.ispartofseries | University Alexandria Engineering Journal; | |
dc.subject | TFET; | en_US |
dc.subject | Gate Leakage Current; | en_US |
dc.subject | Transmission Line Method (TLM); | en_US |
dc.subject | Pseudo-2D; | en_US |
dc.subject | Image Force | en_US |
dc.title | Investigation of gate leakage current in TFET: A semi-numerical approach | en_US |
dc.type | Article | en_US |