A novel technique to enhance the stability and the supply rejection of a Miller compensated LDO

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dc.AffiliationOctober University for modern sciences and Arts (MSA)
dc.contributor.authorM Sinoussi, Nabil
dc.contributor.authorM Elsayed, Ayman
dc.date.accessioned2020-03-09T11:14:10Z
dc.date.available2020-03-09T11:14:10Z
dc.date.issued2009
dc.descriptionMSA Google Scholaren_US
dc.description.abstractA novel technique is utilized to enhance the power supply rejection of a Miller compensated LDO. The frequency compensation tracks the load variations in order to conserve stability across the whole load current range. From a minimum supply of 2.7 V, the LDO provides a regulated 2.4 V output, for a load range of 0-2 mA. The improvement in the supply rejection is at least 10 dB at 2 mA load. At no load, the supply rejection improved by 26 dB. The LDO is simulated using AMS-0.35 m technology.en_US
dc.identifier.citation1. Ka Nang Leung, K. T. Mok Philip, "A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation", IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003. Show Context View Article Full Text: PDF (875KB) Google Scholar 2. S. Sidiropoulos et al., "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers", Symp. VLSI Circuits Dig. Tech. Papers, pp. 124-12, Jun. 2000. Show Context View Article Full Text: PDF (411KB) Google Scholar 3. Elad Alon, Jaeha Kim, "Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops", IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413-424, Feb. 2006. Show Context View Article Full Text: PDF (539KB) Google Scholar 4. A. Rincon-Mora Gabriel, Phillip E. Allen, "A Low-Voltage Low Quiescent Current Low Drop-Out Regulator", IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan. 1998. Show Context Google Scholaren_US
dc.identifier.doihttps://doi.org/10.1109/IDT.2009.5404116
dc.identifier.issnPrint ISSN: 2162-0601
dc.identifier.issnElectronic ISSN: 2162-061X
dc.identifier.otherhttps://doi.org/10.1109/IDT.2009.5404116
dc.identifier.urihttps://t.ly/L19PV
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartofseries4th International Design and Test Workshop (IDT);2009
dc.subjectCapacitorsen_US
dc.subjectFrequencyen_US
dc.subjectEnergy managementen_US
dc.subjectPower system managementen_US
dc.subjectImpedanceen_US
dc.subjectPower suppliesen_US
dc.subjectCircuit simulationen_US
dc.subjectCircuit stabilityen_US
dc.subjectLoad managementen_US
dc.subjectVoltageen_US
dc.titleA novel technique to enhance the stability and the supply rejection of a Miller compensated LDOen_US
dc.typeOtheren_US

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