4-BIT PIPELINE ADC FOR MONOLITHIC ACTIVE PIXEL SENSORS

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dc.AffiliationOctober University for modern sciences and Arts (MSA)
dc.contributor.authorAgieb, Ramy Said
dc.contributor.authorEl Ghitany, Hassan Ahmed
dc.contributor.authorShehata, Khaled Ali
dc.date.accessioned2019-12-04T11:26:41Z
dc.date.available2019-12-04T11:26:41Z
dc.date.issued2009
dc.descriptionAccession Number: WOS:000271545700110en_US
dc.description.abstractLow voltage low power 4-bits 90Ms/s, 40 mu w, with DNL (+0.19/-0.4)LSB and INL (+0.47/-0.46)LSB is designed using 0.13um UMC CMOS technology operated with 1.2V voltage supply. The converter is composed of three stages the first, second stages produce 1.5bit/stage and last stage produce 2 bit/stage. Using Bottom-Plate Switching and fully digital error correction which corrects errors due to capacitor mismatch, charge injection, and comparator offsets. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycleen_US
dc.description.sponsorshipIACSIT Comp Theory & Engn Soc; Modeling & Simulat Soc; IACSITen_US
dc.description.urihttps://www.scimagojr.com/journalsearch.php?q=19700182438&tip=sid&clean=0
dc.identifier.citationCited References in Web of Science Core Collection: 12en_US
dc.identifier.isbn978-0-79180-297-7
dc.identifier.urihttps://cutt.ly/ue3HczJ
dc.language.isoenen_US
dc.publisherAMER SOC MECHANICAL ENGINEERSen_US
dc.relation.ispartofseries2nd International Conference on Advanced Computer Theory and Engineering (ICACTE 2009);
dc.subjectOctober University for University for pipeline ADCen_US
dc.subject1.5 bit/stageen_US
dc.subjectdigital error correctionen_US
dc.subjectbottom-plate switchingen_US
dc.title4-BIT PIPELINE ADC FOR MONOLITHIC ACTIVE PIXEL SENSORSen_US
dc.typeBook chapteren_US

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