4-BIT PIPELINE ADC FOR MONOLITHIC ACTIVE PIXEL SENSORS
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Date
2009
Journal Title
Journal ISSN
Volume Title
Type
Book chapter
Publisher
AMER SOC MECHANICAL ENGINEERS
Series Info
2nd International Conference on Advanced Computer Theory and Engineering (ICACTE 2009);
Doi
Scientific Journal Rankings
Abstract
Low voltage low power 4-bits 90Ms/s, 40 mu w, with DNL (+0.19/-0.4)LSB and INL (+0.47/-0.46)LSB is designed using 0.13um UMC CMOS technology operated with 1.2V voltage supply. The converter is composed of three stages the first, second stages produce 1.5bit/stage and last stage produce 2 bit/stage. Using Bottom-Plate Switching and fully digital error correction which corrects errors due to capacitor mismatch, charge injection, and comparator offsets. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycle
Description
Accession Number: WOS:000271545700110
Keywords
October University for University for pipeline ADC, 1.5 bit/stage, digital error correction, bottom-plate switching
Citation
Cited References in Web of Science Core Collection: 12