Modifying the logic gate symbols to enrich the designing of the computer systems by 3-D bit-matrices

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dc.AffiliationOctober University for modern sciences and Arts (MSA)
dc.contributor.authorBadr, Assem)
dc.date.accessioned2019-11-18T08:13:35Z
dc.date.available2019-11-18T08:13:35Z
dc.date.issued2018-12
dc.descriptionAccession Number: WOS:000454548400252en_US
dc.description.abstractRecently, the most computer and digital systems are built based on the parallelism to increase their speed of processing. The complications of these systems are increasing proportionally with the complexity of the used parallelism methodologies. According to the growing of this complexity, this research proposes a modification to enhance designing tasks by the concept of the 3-dimensions easily. This research introduces a novel terminology called "Bit-Vector-Matrix". Moreover, this research modifies the standard logic symbols beside reformulates their conventional Boolean algebraic expressions to become more convenient and compatible with the "Bit-Vector-Matrix". We proposed novel logic gate symbols called "Peer-logic-gates". They are useful for representing the intensive concurrent logical operations through intensive parallel digital buses in computer systems. In addition, they will be a promising teaching tool to instruct many computer courses. This paper constructed based on the deterministic algorithm, realized using VHDL codes and evaluated by the reliable simulator "Modelsim". (C) 2018 Ain Shams University.en_US
dc.description.urihttps://www.scimagojr.com/journalsearch.php?q=19700200705&tip=sid&clean=0
dc.identifier.citationWebsite https://software.intel.com/en-us/blogs/2013/avx-512-instructions By James R. (Intel), published on July 23, 2013, updated June 20, 2017, March 9, 2018. Google Scholar [2] Oliveira Gustavo Prado, de Assumpção Drummond Lucia M, Boaventura Ricardo Soares, Yamanaka Keiji. Evaluating performance of deterministic algorithms on a multicore processor of a public cloud. In: IEEE international symposium on computer architecture and high performance computing workshop, 2014. Google Scholar [3] Ayaz ul Hassan, Mayez Al- Mouhamed, Allam Fatayer, N. Mohammad Optimizing the matrix multiplication using strassen and winograd algorithms with limited recursions on many-core Int J Parallel Prog (2016) August Google Scholar [4] Randal E. Bryant Graph-based algorithms for Boolean function manipulation Trans Comput, C-35-8 (1986), pp. 677-691 IEEE CrossRefView Record in ScopusGoogle Scholar [5] Chattopadhyay A, Amar L, Soeken M, Gaillardon P, De Micheli G. Notes on Majority Boolean algebra, IEEE; 2016. Google Scholar [6] Haitao Zhang, Guoqiang Li, Daniel Sun, Lu Yonggang, Ching-Hsien Hsu Verifying cooperative software, a SMT-based bounded model checking approach for deterministic scheduler J Syst Archit (2017)en_US
dc.identifier.doihttps://doi.org/10.1016/j.asej.2018.06.002
dc.identifier.issn2090-4479
dc.identifier.otherhttps://doi.org/10.1016/j.asej.2018.06.002
dc.identifier.urihttps://www.sciencedirect.com/science/article/pii/S2090447918300480
dc.language.isoen_USen_US
dc.publisherELSEVIER SCIENCE BVen_US
dc.relation.ispartofseriesAIN SHAMS ENGINEERING JOURNAL;Volume: 9 Issue: 4 Pages: 3207-3216
dc.relation.urihttps://cutt.ly/xeJUNpR
dc.subjectUniversity for October University for Matricesen_US
dc.subjectBoolean algebraen_US
dc.subjectMicroprocessorsen_US
dc.subjectVHDL moduleen_US
dc.subjectDeterministic algorithmen_US
dc.subjectModelsen_US
dc.titleModifying the logic gate symbols to enrich the designing of the computer systems by 3-D bit-matricesen_US
dc.typeArticleen_US

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