Gate Dielectric Constant Engineering for Alleviating Ambipolar Conduction in MOS-GNRFET

Abstract

In the current study, a gate dielectric constant engineering approach is reported to minimize the ambipolar conduction in MOSFET-Like Graphene Nano Ribbon (MOS-GNRFET). The dielectric constants, k, over different regions of the device play a crucial role in energy band diagram modification. So, by choosing suitable values of k over the drain, channel and source regions, the band-to-band tunneling (BTB) path at the drain–channel interface can be minimized. Subsequently, the ambipolar current in MOS-GNRFET is decreased substantially. In addition, the high frequency performance is investigated considering the cutoff frequency, fT, as a figure of merit. It has been found that the proposed technique reduces the ambipolar current by about four orders, decreases OFF-current by two orders and consequently increases ON/OFF current ratio by two orders giving a value of 2.9 × 1010. It has been found that the proposed technique does not deteriorate the gate capacitance which, in turn, enhances fT that reaches about 23 THz, making the proposed structure efficient for digital and analog performance.