Abstract:
This study presents a 2-D analytical model for the double gate tunnel FET (DG-TFET). The model considers the gate-on-source overlap that may occur intentionally or unintentionally due to fabrication tolerances. The 2-D Poisson's equation is solved in the main four regions of the structure, namely, the source, channel, drain, and the overlapped region inside the source. The mobile charge inside the channel is taken into consideration. In addition, the source and the drain depletion region lengths are precisely calculated by an iterative technique. Such crucial assumptions and calculations result in accurate expectations of the electrostatic potential. The energy band diagram could be extracted according to the obtained electrostatic potential, and, subsequently, the minimum tunneling width is computed. The impact of channel length and the overlap distance is thoroughly investigated. The results of the proposed model and Silvaco TCAD simulations are compared. The comparison satisfies a good agreement that verifies the validity of the presented model. © 2021 IEEE.
