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| dc.contributor.author | Badr, Assem) | |
| dc.date.accessioned | 2019-11-18T08:13:35Z | |
| dc.date.available | 2019-11-18T08:13:35Z | |
| dc.date.issued | 2018-12 | |
| dc.identifier.citation | Website https://software.intel.com/en-us/blogs/2013/avx-512-instructions By James R. (Intel), published on July 23, 2013, updated June 20, 2017, March 9, 2018. Google Scholar [2] Oliveira Gustavo Prado, de Assumpção Drummond Lucia M, Boaventura Ricardo Soares, Yamanaka Keiji. Evaluating performance of deterministic algorithms on a multicore processor of a public cloud. In: IEEE international symposium on computer architecture and high performance computing workshop, 2014. Google Scholar [3] Ayaz ul Hassan, Mayez Al- Mouhamed, Allam Fatayer, N. Mohammad Optimizing the matrix multiplication using strassen and winograd algorithms with limited recursions on many-core Int J Parallel Prog (2016) August Google Scholar [4] Randal E. Bryant Graph-based algorithms for Boolean function manipulation Trans Comput, C-35-8 (1986), pp. 677-691 IEEE CrossRefView Record in ScopusGoogle Scholar [5] Chattopadhyay A, Amar L, Soeken M, Gaillardon P, De Micheli G. Notes on Majority Boolean algebra, IEEE; 2016. Google Scholar [6] Haitao Zhang, Guoqiang Li, Daniel Sun, Lu Yonggang, Ching-Hsien Hsu Verifying cooperative software, a SMT-based bounded model checking approach for deterministic scheduler J Syst Archit (2017) | en_US |
| dc.identifier.issn | 2090-4479 | |
| dc.identifier.other | https://doi.org/10.1016/j.asej.2018.06.002 | |
| dc.identifier.uri | https://www.sciencedirect.com/science/article/pii/S2090447918300480 | |
| dc.description | Accession Number: WOS:000454548400252 | en_US |
| dc.description.abstract | Recently, the most computer and digital systems are built based on the parallelism to increase their speed of processing. The complications of these systems are increasing proportionally with the complexity of the used parallelism methodologies. According to the growing of this complexity, this research proposes a modification to enhance designing tasks by the concept of the 3-dimensions easily. This research introduces a novel terminology called "Bit-Vector-Matrix". Moreover, this research modifies the standard logic symbols beside reformulates their conventional Boolean algebraic expressions to become more convenient and compatible with the "Bit-Vector-Matrix". We proposed novel logic gate symbols called "Peer-logic-gates". They are useful for representing the intensive concurrent logical operations through intensive parallel digital buses in computer systems. In addition, they will be a promising teaching tool to instruct many computer courses. This paper constructed based on the deterministic algorithm, realized using VHDL codes and evaluated by the reliable simulator "Modelsim". (C) 2018 Ain Shams University. | en_US |
| dc.description.uri | https://www.scimagojr.com/journalsearch.php?q=19700200705&tip=sid&clean=0 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | ELSEVIER SCIENCE BV | en_US |
| dc.relation.ispartofseries | AIN SHAMS ENGINEERING JOURNAL;Volume: 9 Issue: 4 Pages: 3207-3216 | |
| dc.relation.uri | https://cutt.ly/xeJUNpR | |
| dc.subject | University for October University for Matrices | en_US |
| dc.subject | Boolean algebra | en_US |
| dc.subject | Microprocessors | en_US |
| dc.subject | VHDL module | en_US |
| dc.subject | Deterministic algorithm | en_US |
| dc.subject | Models | en_US |
| dc.title | Modifying the logic gate symbols to enrich the designing of the computer systems by 3-D bit-matrices | en_US |
| dc.type | Article | en_US |
| dc.identifier.doi | https://doi.org/10.1016/j.asej.2018.06.002 | |
| dc.Affiliation | October University for modern sciences and Arts (MSA) |
