dc.contributor.author |
Agieb, Ramy Said |
|
dc.contributor.author |
El Ghitany, Hassan Ahmed |
|
dc.contributor.author |
Shehata, Khaled Ali |
|
dc.date.accessioned |
2019-12-04T11:26:41Z |
|
dc.date.available |
2019-12-04T11:26:41Z |
|
dc.date.issued |
2009 |
|
dc.identifier.citation |
Cited References in Web of Science Core Collection: 12 |
en_US |
dc.identifier.isbn |
978-0-79180-297-7 |
|
dc.identifier.uri |
https://cutt.ly/ue3HczJ |
|
dc.description |
Accession Number: WOS:000271545700110 |
en_US |
dc.description.abstract |
Low voltage low power 4-bits 90Ms/s, 40 mu w, with DNL (+0.19/-0.4)LSB and INL (+0.47/-0.46)LSB is designed using 0.13um UMC CMOS technology operated with 1.2V voltage supply. The converter is composed of three stages the first, second stages produce 1.5bit/stage and last stage produce 2 bit/stage. Using Bottom-Plate Switching and fully digital error correction which corrects errors due to capacitor mismatch, charge injection, and comparator offsets. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycle |
en_US |
dc.description.sponsorship |
IACSIT Comp Theory & Engn Soc; Modeling & Simulat Soc; IACSIT |
en_US |
dc.description.uri |
https://www.scimagojr.com/journalsearch.php?q=19700182438&tip=sid&clean=0 |
|
dc.language.iso |
en |
en_US |
dc.publisher |
AMER SOC MECHANICAL ENGINEERS |
en_US |
dc.relation.ispartofseries |
2nd International Conference on Advanced Computer Theory and Engineering (ICACTE 2009); |
|
dc.subject |
October University for University for pipeline ADC |
en_US |
dc.subject |
1.5 bit/stage |
en_US |
dc.subject |
digital error correction |
en_US |
dc.subject |
bottom-plate switching |
en_US |
dc.title |
4-BIT PIPELINE ADC FOR MONOLITHIC ACTIVE PIXEL SENSORS |
en_US |
dc.type |
Book chapter |
en_US |
dc.Affiliation |
October University for modern sciences and Arts (MSA) |
|