Ahmed, Mahmoud AymenEl-Bendary, M. A. MohamedAmer, Fathy Z.Singy, Said M.2019-11-302019-11-302019Cited References in Web of Science Core Collection: 6978-1-5386-5261-9https://ieeexplore.ieee.org/document/8646550Accession Number: WOS:000462976100089Arithmetic Logic Unit (ALU) is an essential building block in many applications such as microprocessors, DSP, and image processing, while power efficiency is a general concern in VLSI design. This paper presents Delay time optimization of 4-bit ALU designed using full-swing gate diffusion input (GDI) technique. Simulations carried out in Cadence virtuoso using 65nm TSMC processes with a supply voltage of 1.2 volts and a frequency of 125 MHz, Simulation results revealed improvement in Delay time and overall Energy of the optimized ALU designenOctober University for University for Arithmetic Logic Unit (ALU)Gate Diffusion Input (GDI)Full-Swing GDI (FS-GDI)Book chapter